1. Field of the Invention
Embodiments of the invention generally relate to semiconductor processing technologies and, more specifically, to methods for fabricating a substrate containing dual damascene structures having low dielectric constant material thereon.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The demand for greater circuit density necessitates a reduction in the dimensions of the integrated circuit components, e.g., sub-micron dimensions and the use of various materials to fabricate devices in order to achieve much faster and better electrical performance, such as materials with higher conductivity used in metal lines, materials with lower permittivity (low-k) dielectric constant used as insulating materials, etc. For integrated circuit fabrication, metal interconnects with low resistance, such as copper and aluminum interconnects, provide conductive paths between the integrate circuit components on integrated circuit devices. Generally, metal interconnects are electrically isolated from each other by a dielectric bulk insulating material.
Some integrated circuit components include multilevel interconnect structures, for example, dual damascene structures. Typically, dual damascene structures have dielectric bulk insulating layers, semiconductive layers, low dielectric constant material layers, and conductive metal layers, such as conductive copper layers, stacked on top of one another. Vias and/or trenches are etched into the dielectric bulk insulating layer, and the conductive metal layers are subsequently filled into the vias and/or trenches and planarized, such as by a chemical mechanical planarization process (CMP), so that the conducting metal materials are left in the vias and/or trenches. In the dual damascene approach, a rather complex dielectric stack that includes a sequence of hard mask, low-k dielectrics, and etch stop layers, etc., may be required. In addition, via lithography and patterning as well as trench lithography and patterning are required for fabricating the complex dielectric stack before filling the vias and the trenches with the conductive metal materials.
Different schemes to process a substrate containing dual damascene structures have been proposed. FIG. 1 is one example of a dual damascene structure having vias and trenches in a dielectric stack film stack 150 with micro-loading problems after trench etching. The dielectric stack film stack 150 is formed over a substrate 100 having a dielectric base layer 134 and a first layer of metal lines 140 formed thereon. The dielectric stack 150 may include a bottom barrier layer, one or more dielectric bulk insulating layers, and an optional middle etch stop layer. A top layer 122 may be deposited above the dielectric film stack 150 to protect the underlying dielectric film stack 150. The top layer 122 may be a capping layer, a hard mask layer, a dual hard mask layer, an etch stop layer, or a polish stop layer. The dielectric film stack 150 is generally made of a low dielectric constant (e.g., κ lower than 4) material for a copper dual damascene structure. The bottom barrier layer 130 can be silicon nitride, silicon carbide, silicon oxycarbide, or low k barrier materials. The top layer 122 typically includes silicon oxy-nitride (SiON), tetra-ethyl-ortho-silicate (TEOS) based oxide, silicon carbide, silicon dioxide, silicon nitride, silicon oxycarbide, and the like.
In a via first dual damascene fabrication scheme, via lithography and via etching and patterning are performed through the dielectric film stack 150 and stopped at the bottom barrier layer 130. A trench lithography process is then performed on top of the dielectric film stack 150 to transfer trench pattern from the top layer 122 to the dielectric film stack 150, perform trench etching therein, and define trench openings. Variations of the via first scheme may additionally include a bottom anti-reflective coating (BARC) layer to fill via openings and cover the dielectric film stack 150 before the trench lithography process. Additionally, a hard mask layer may be deposited over the BARC layer to serve as an etch mask layer in order to form trenches through lithography, patterning and BARC etching.
The dielectric film stack 150 may have a dense region with small critical dimension and high feature density (e.g., dense vias 168) and an open area with large critical dimension and low feature density (e.g., isolated vias 160). A major issue with a dual damascene fabrication process with no middle trench etch stop is that it is difficult to control the etch depth across features of different critical dimensions such that there is uneven trench etch depth between the dense area and open area. Many etching processes and chemistries manage to maintain a good etch profile without micro trenching; however, micro-loading problems invariably arise where the open area with large critical dimension are etched faster than the dense area with small critical dimension. For example, trench etching within the dielectric film stack 150 usually results in micro-loading such that trenches 170 in the open area with large critical dimension are etched faster than trenches 178 in the dense area with small critical dimension. As a result, the etch depths for trenches 170, “A”, are usually larger than the etch depths for trenches 178, “B”, with the difference as “D”. Since a typical metal interconnect level includes critical dimensions of various sizes, the problems with micro-loading create a disparity in trench depth in relation with feature sizes, and ultimately poor sheet resistance control of the integrated circuit devices.
Therefore, there is a need for a method of uniformly fabricating a dual damascene structure to form a desired dimension and profile of material stacks and to control the etch depths in the vias and trenches.